HARDWARE HUB

27 June 2026 22:45

DDR6 Desktop and Server Memory Could Reach 17,600 MT/s [Guru3D]
https://ift.tt/P2rYZ7t

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HARDWARE HUB

27 June 2026 14:45

Could Intel Save Gamers? Arc B770, We Have One (Sort Of)
https://youtu.be/D-XceWITCQg

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HARDWARE HUB

27 June 2026 07:45

Apple seeks to buy memory chips from blacklisted Chinese company
https://ift.tt/7FCJql6

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HARDWARE HUB

27 June 2026 04:45

Semafor: "Exclusive: Qualcomm plans new chip architecture for phones"
https://ift.tt/Xvufktp

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HARDWARE HUB

26 June 2026 11:45

IBM Unveils New Method to Make Smaller Computer Chip Parts
https://ift.tt/gXxAQcf

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HARDWARE HUB

26 June 2026 04:45

Zen 6 Desktop Ryzen CPUs Reportedly Lack Integrated GPU - HWCooling.net
https://ift.tt/sPcrLVm

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HARDWARE HUB

26 June 2026 03:45

A Deep Dive On China’s “LineShine” All-CPU, Exaflops-Class Supercomputer
https://ift.tt/ZI5qS01

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HARDWARE HUB

25 June 2026 22:45

French retailer mocks €1039 Steam Machine with “Stim Machine” RX 9060 XT PC for €999
https://ift.tt/PXHRatg

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HARDWARE HUB

25 June 2026 16:45

Future Transistor Stacking Plans Start to Diverge | IBM chooses a different path from Intel, Samsung, and TSMC
To construct CFETs, Intel, Samsung, and TSMC are pursuing a scheme called a monolithic process. Fundamentally, that means they are building both the top and bottom device at the same time, one directly above the other. IBM, in contrast, is committed to a scheme that’s generally called a sequential process, because it builds a complete layer of transistors before constructing another layer above it. https://spectrum.ieee.org/cfet-ibm-plan

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HARDWARE HUB

25 June 2026 15:45

Apple Just Increased Prices: Here's What's Changed
https://ift.tt/4boZnyQ

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HARDWARE HUB

25 June 2026 06:45

Micron locks in historically high memory prices for five years
https://ift.tt/7ImxN9y

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HARDWARE HUB

25 June 2026 02:45

[The Phawx] The DEFINITIVE Review - MSI Claw 8 Ex Ai+
https://www.youtube.com/watch?v=yX6DdzzLo7o

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HARDWARE HUB

24 June 2026 22:45

DeviceTree-ACPI Hybrid Mode Proposed by Qualcomm ( Hans de Goede ) For Improving Linux Support On current Snapdragon Laptops. ACPI only for future generations
https://ift.tt/O5QD9p8

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HARDWARE HUB

24 June 2026 18:45

OpenAI has its own inference chip now.
https://ift.tt/S40gcFs

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HARDWARE HUB

24 June 2026 16:45

Valve Says Steam Deck 2 Is Getting Closer, but Still Not Ready Yet
https://ift.tt/iIBGKXR

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HARDWARE HUB

27 June 2026 16:45

Could lightweight game specific AI adapters become the next step for handheld upscaling, especially when rendering from extremely low resolutions?
This is more of a thought experiment than a proposal, and I'm curious whether I'm overlooking something fundamental.After spending quite a bit of time with my Legion Go, one thing that surprised me is how good 800p can look on an 8.8 inch display. It made me wonder whether handhelds deserve a different AI upscaling strategy than desktop GPUs.As handheld hardware tries to keep up with future AAA games, internal rendering resolutions may need to drop even further. Reconstructing a convincing 800p or 1080p image from something like 360p could have an enormous payoff because every saved GPU cycle matters on a tiny APU.I know AMD is already working on lighter weight versions of FSR4 for handhelda, but that's not quite what I'm suggesting.What if AMD and Nvidia built support directly into DLSS or FSR for lightweight game specific adapters? Rather than training a new model, developers could generate a small specialization layer using the existing toolchain that learns a game's rendering characteristics, temporal behavior, and visual style.The goal wouldn't just be higher image quality. The hope would be to achieve similar or better quality at lower compute, potentially extending the useful life of small APUs. Similar approaches have worked well in other areas of AI, where a lightweight expert/specialization model can overperform a strong general model.Maybe the gains would be too small to justify the added complexity, or maybe AMD and Nvidia have already explored this internally. While handhelds are what made me think about this, the same idea could theoretically benefit desktop GPUs as well. Handhelds just seem like the environment where the tradeoffs are most compelling.Has anything like this been explored publicly, or is there a fundamental reason why a lightweight game specific adapter wouldn't provide meaningful benefits over current universal AI upscalers?

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HARDWARE HUB

27 June 2026 12:45

Apple will skip its high-end M6 Mac chips and fast-track an AI-focused M7 generation for 2027, report claims — may release a base M6 chip for entry-level Macs this year
https://ift.tt/gUuP6nc

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HARDWARE HUB

27 June 2026 07:45

Samsung readies $648 billion bet, report says, as AI boom reshapes South Korea
https://ift.tt/O9L5ydb

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HARDWARE HUB

27 June 2026 00:45

China’s CXMT Is Set to Challenge DRAM Incumbents
https://ift.tt/IJsCymw

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HARDWARE HUB

26 June 2026 05:45

MSI Claw 8 EX AI+ review roundup: Unmatched power, unhinged price
https://ift.tt/qdi7unP

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HARDWARE HUB

26 June 2026 03:45

IBM Outlines Sub-1nm Nanostack Transistor Technology: Building the Next Gen By Going Up
https://ift.tt/0FtWOzp

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HARDWARE HUB

26 June 2026 01:45

Jim Keller on Tenstorrent’s BlackHole Scaling and IPO Ambitions - EE Times
https://ift.tt/nb3260Q

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HARDWARE HUB

25 June 2026 20:45

Microsoft Announces Significant Price Rises for Xbox Series X and S, 2TB Model Discontinued
https://ift.tt/aWDCkXu

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HARDWARE HUB

25 June 2026 15:45

IBM's 0.7nm NanoStack Claims 50% Performance Gain Over 2nm
The chip industry has been telling investors and governments for years that the laws of physics are running out of room. IBM's announcement of a 0.7 nanometer architecture, described in detail on [IBM's research newsroom](https://newsroom.ibm.com/2026-06-25-ibm-debuts-worlds-first-sub-1-nanometer-chip-technology), suggests there is at least a decade more road ahead.The core claim is architectural, not just a size number. IBM calls the design "nanostack," a 3D nanosheet approach that vertically stacks and staggers transistors, allowing different materials to be used in each layer for independent performance and efficiency tuning. The result, IBM says, is a fingernail-sized chip carrying nearly 100 billion transistors, roughly double the density of its 2021-era 2nm design, with up to 50% performance improvement and 70% greater energy efficiency over that baseline."With our new nanostack architecture, we're not just making smaller transistors, we're reinventing how chips are built," said Jay Gambetta, IBM Research Director and IBM Fellow. The company is backing the research with physical infrastructure: its Albany, New York facility will house High NA EUV lithography equipment from ASML, developed collaboratively with Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions.The honest caveat is that IBM's semiconductor research announcements and their manufacturing reality operate on very different timelines. IBM's own projection here is "within 5 years" for production feasibility, a number to hold loosely, and the announcement does not name a major foundry manufacturing partner. IBM's research division does not run a consumer fab, so the path from Albany lab result to production silicon involves parties not yet identified.For teams building AI infrastructure, the 50% performance and 70% energy efficiency claims are the numbers worth tracking, alongside which foundry eventually commits to the nanostack architecture. IBM estimates at least a decade of continued scaling potential with this approach, which matters more for long-term chip roadmap planning than the headline node number.Our coverage: https://aiweekly.co/alerts/ibms-07nm-nanostack-claims-50-performance-gain-over-2nm

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HARDWARE HUB

25 June 2026 10:45

Qualcomm HBC ("high bandwidth compute")
https://preview.redd.it/sqint6o4rd9h1.png?width=2141&format=png&auto=webp&s=082fa675263283e40d33bd53b6b4cb465e7f91bfTLDR -> is the accelerator just a glorified memory controller, somewhat?Qualcomm presented in their 2026 investor day a new form of technology (which looks very odd to me because it's staking Memory on top of Logic), which they brand/market as "HBC" aka High Bandwidth Compute.Logic will do some form of computations and have some SRAM for register files etc. But heat will get trapped because thermal needs to get radiated out somehow.HBM is sticking of DDR memory (12-16 layers high) and using a base silicon interposer for the signal bus routing (1024 bits bus) over into the SOC.In Qualcomm's slide they replace it with LP-DDR (which is still DDR but with a narrower bus-width and maybe the memory controller uses lower power).And since it shows TSV, which means the holes drilled into the memory stacks are most likely stagger left-right-left (Top layer 0 -> 16 bits left, layer 1 ->16 bits right, layer 2 -> left with some offsets).That increase memory capacity (e.g. total 256GB LPDDR stack) but memory bandwidth will still be low.That brings me to the part where it seems like the accelerator will do some math compute and just send across to the SOC the necessary results or reducing data movement size (in GB bytes). Essentially doing some "prep" work and then routing the "optimized data" over to the SOC.Because it's optimized it can reduce the "total overall" data footprint that needs to be routed. Moving data consumes more energy, so the lower amount of bytes i move the lower the energy measuring using pico-joules per bitTCO -> Lower
(technically correct, since you don't need interposer for that big of signal routing to the SOC compared to HBM usage)Energy -> Lower
(technically correct, because using LPDDR and a narrower memory bus to the SOC lowers pico-joules per bit)ComplexityFor the accelerator to work, i can see a complexity in the software aspect (maybe LLM or coding agent can help reduce some of that mess).Need to figure what kind of computation the accelerator is design for?Talking to the SOC on what the accelerator have to send over and memory address (physical System Level Cache ("SLC"). The bulk of the workload is still handle on the SOC directly since it gets better thermal dissipation.

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HARDWARE HUB

25 June 2026 04:45

Qualcomm and Meta Announce Strategic Multi-Generation Agreement on Data Center CPUs
https://ift.tt/gOU07jR

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HARDWARE HUB

24 June 2026 22:45

Samsung Electronics Allocates Half HBM Production to HBM4
https://ift.tt/2AMgskt

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HARDWARE HUB

24 June 2026 18:45

Steam Machine: Hardly any cheaper gaming PCs, 8 GiByte is enough - Valve in interview
https://ift.tt/6bdeLtf

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HARDWARE HUB

24 June 2026 17:45

Chinese Supercomputer Outpaces US Rivals
https://ift.tt/xoeAb8j

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HARDWARE HUB

24 June 2026 15:45

Visual examination suggests a rather inexperienced prompt writer for an AI image generator instructed it to make the viral ROG Equalizer 12V-2x6 contacts look “burnt,” without first looking at how a genuinely overheated connector actually changes.
https://ift.tt/Qa9GHDP

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